UAV Tasks deployment

This problem deals with Unmanned Aerial Vehicle (UAV). A key functionality of the UAV is its ability to detect obstacles and plan a new trajectory that will allow it to avoid the UAV while continuing its path to the desired destination. This function composed of obstacle detection, decision making and calculation of a new trajectory must be ensured by the drone alone, without intervention from the ground station, in order to gain in efficiency. It must also be optimized to adapt to the drone’s energy resources. The obstacle detection and avoidance functionality is provided by a platform using a heterogeneous multi-core architecture (SHMC), which allows the UAV to have a high computing power while reducing its energy consumption. The SHMC processor is composed of cores with different computing power but using the same instruction set. A core can thus be allocated to any software task, without the need for recompilation. The cores can also be shut down when they are not allocated to any task, without the need to be kept in a sleep mode.  On this type of processor we generally find a set of more powerful cores (Big Core) and a set of less powerful cores (Little Core). The platform used for the case study is  composed of four Cortex A15 cores called « BigCore » and four Cortex A7 cores called « LittleCore ».

The problem consists of deploying ten tasks (image acquisition, filtering, obstacle detection, …) on a maximum of 8 processors (cores) by satisfying a set of constraints.

A task is characterized by:

– a memory size required for its execution (MemorySize)

– a period (Period)

– two WCET (Worst Case Execution Time) depending on whether the task is performed by a Big Core (WCETBC) or a Little Core (WCETLC).

The problem description comes from [1]. A full description of the adressed problem and of the related DEPS models is available in section 9.2. of [2] and here too.